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# Three NAND gates are connected as shown in circuit. The logic operation corresponds to

$(a)\;OR\;gate \\ (b)\;AND\;gate \\ (c)\;NOR\;gate \\ (d)\;XOR\;gate$

$Y_1 =\overline {A.A} =\bar {A}$
$Y_2 =\overline {B.B} =\bar {B}$
$Y= \overline {\bar {A}. \bar {B}}=A+B$